In any integrated circuit (IC) employing multiple automatic gain control (AGC) stages, a tradeoff is typically made when setting the gain in the different stages. For example, in a wireless communication system, the receiver may employ two AGC stages. The output of the first AGC stage is mixed with an intermediate carrier frequency signal to step it down to the baseband frequency. The baseband signal is then filtered. The filtered signal is passed through a second AGC stage. The distribution of the total gain between these two AGC stages has an impact upon the noise figure and the intermodulation distortion.
The noise figure is the measure of the noise introduced by the receiver. The noise figure will determine the ability of the receiver to process weak signals. The intermodulation distortion will determine the receiver's ability to process strong signals.
In general, a system which has little attenuation of the input signal before an active gain stage will have a superior noise figure but may be susceptible to interference due to intermodulation distortion. On the other hand, a system which attenuates the input signals before application to the active gain stages will have superior intermodulation performance since the signal level at the active gain stages will be lower. Unfortunately this attenuation will add to the noise figure and thus reduce the system's sensitivity to weak signals.
In designing an IC, accommodating for this classic tradeoff between the noise figure and intermodulation distortion can become very expensive and time consuming. If the proper balance cannot be reached for the many different users of the IC, then many versions of the IC may have to be created and maintained. Additionally, in attempting to adapt the IC to a particular application, the tradeoff may have to be changed as the system design progresses. In this case the IC will need to be modified each time a new tradeoff is identified. Inasmuch as an IC fabrication cycle is on the order of 8 weeks, redesigning the IC introduces a substantial delay in the development of the system IC and adds significantly to the engineering cost.
Accordingly it is desirable to provide a more flexible IC design for systems employing multiple AGC stages.